In particular, it does a terrific job on FFTs. This paper by Analog Devices will probably help me understand what is happening. The block diagrams, especially figure 6. Quote from: SMB on June 30, , pm. This seems to simulate OK. You will need to parameterize the widths of the inputs and registers. Quote from: SMB on July 01, , pm. Getting closer see attachment! Still some overflow, and the sine lookup is clearly inverted, but its getting there.
It turns out that if you use non-blocking assignments, the output is garbage, but blocking assignments make it work. Was that a conscious choice on your part, or just serendipity that it worked out as it was supposed to? Quote from: SMB on July 02, , am. So I coded up a few things and tested. This Verilog version gives identical results to the VHDL version - set up to use bit signed samples. Quote from: SMB on July 02, , pm. Ok, so I almost have it completely correct. The first problem with the sine wave was that in the sinewave routine I was already shifting its output so that it would have an average of half the dynamic range 2.
Removing that shift routine fixed the sine wave. Second thing to say is that the accumulators need to be tuned by adding or subtracting a specific amount so that the waveforms take up the whole output dynamic range but dont overflow. It's hard to tell what exactly is wrong as we don't see your whole code and one hidden part was already one source of your problems! But from the look of what you get, I guess it might still be overflowing.
Have you tried with a wider accumulator width? On the other hand, if the reference voltage is less than or equal to the output of integrator , comparator is adapted to output a second value e. As discussed above, in one embodiment, DAC is adapted to provide a positive or negative charge based on such an output. Comparator is described in further detail below in conjunction with FIG. Digital integrator , in one embodiment, is a digital delta-sigma integrator that is adapted to integrate the output values produced by comparator over a specified integration period.
In one embodiment, integrator is adapted to perform the integration by adding each output of comparator to an accumulator. Accordingly, the value in the accumulator is incremented when comparator outputs a logical one, and not adjusted when comparator outputs a logical zero. In one embodiment, integrator is adapted to provide the current value of the accumulator to integrator each time integrator receives an output from comparator At the end of the integration period, integrator , in one embodiment, is adapted to reset the accumulator.
Digital integrator is described in further detail below in conjunction with FIG. Digital integrator , in one embodiment, is adapted to perform a second integration based on the output of integrator over the specified integration period. To perform the second integration, in one embodiment, integrator is adapted to add each output of integrator to another accumulator. At the end of the integration period, integrator , in one embodiment, is adapted to reset the accumulator in conjunction with the resetting of integrator 's accumulator.
In the illustrated embodiment, the output of integrator is provided to register map In some embodiments, the integrator is adapted to store the output in a buffer before providing it to register map In some embodiments in which ADC is not being used for optical sensing, the output of integrator may be coupled to other suitable destinations.
As discussed above, in some embodiments, ADC may be used in conjunction with sensor In one embodiment, if sensor is implementing a proximity sensor, ADC may be adapted to improve the performance of the sensor, e. As will be described in conjunction with FIGS. As shown, diagram includes photodiodes - and switches and In some embodiments, photodiode corresponds to infrared radiation IR photodiode , and photodiodes and collectively correspond to visible diode In some embodiments, switches and are implemented within AMUX In the illustrated embodiment, switches and are adapted to couple photodiode and photodiodes and to node Note that the illustrated embodiment uses no anti-aliasing or input current amplifiers between the photodiodes and ADC This in conjunction with charge measuring may produce a relatively low-noise ADC in some instances.
In some embodiments, an amplifier or other appropriate or desired circuit may be included between photodiodes - and node , albeit at the expense of added noise. Photodiode , in one embodiment, has a strong infrared radiation IR response. In the illustrated embodiment, if photodiode is selected, photodiode is adapted to source negative current from node with increasing light.
In some embodiments, photodiode is used for proximity detection or measurement. In one embodiment, photodiode may have an infrared optical filter placed above the diode. Photodiodes and , in one embodiment, are stacked to form an ambient-light-sensing ALS dual photodiode. In one embodiment, photodiodes and may have a green optical filter to create a response that is closer to a photopic response.
In some embodiments, photodiodes and are diffusion devices that have a relatively slow speed e. In one embodiment, photodiode has a strong IR response, and is adapted to source negative current with increasing light. In one embodiment, when photodiode is selected, the Nwell in which it resides is biased to a positive voltage, and photodiode outputs a positive current with increasing light.
As discussed above, DAC is one embodiment of a DAC that is adapted to generate positive and negative charges that are asymmetric. Charge delivered is the product of capacitance and discharge voltage. This then results in a net change of 1. This then results in a net change of 2. This is a voltage doubler structure but it does not double the discharge voltage to 1. In one embodiment, this results in the positive charge being about three times greater than the negative charge.
As will be described below, DAC is adapted to generate asymmetric charges by using a positive charge pump to increase an input voltage and by using a negative charge pump to invert an input voltage.
In some instances, DAC has less capacitance, lower noise, and less inaccuracy due to reference-supply pattern-dependent settling, and provides increased useable range on unidirectional photodiode signals e.
Higher signal resolution may also be obtained for the same number of integrator bits over that of a symmetric DAC. In many instances, symmetric DACs waste half the range on unidirectional signals. This then allows the DAC to contribute less noise at low signals where the shot noise is low but still accommodate larger signals without loss of resolution due to insufficient bits of resolution. In addition, using the voltage doubler structure, in some embodiments, allows use of smaller capacitors that may be half the size for non-voltage doubler DAC structures.
This may also reduce the switch-capacitor-noise power by the same amount. The voltage doubling switching may not add additional noise provided that the voltage source is moderately low noise. In the illustrated embodiment, DAC includes a positive charge pump and a negative charge pump Positive charge pump , in one embodiment, is adapted to generate a positive charge that drives a current from DAC to node In the illustrated embodiment, charge pump is adapted to generate the positive charge, by using voltage source B to charge one or both of capacitors A and B.
Once charged, capacitors are then coupled in series with voltage source C to produce a higher voltage. In one embodiment, if sources B and C provide the same voltage e.
In one embodiment, positive charge pump is adapted to adjust the amount of capacitance used to generate the positive charge based on the strength of the input current of ADC In one embodiment, if the input current is within a stronger range e.
By increasing the effective capacitance, charge pump generates a stronger charge for preventing overloading, but produces greater noise.
On the other hand, if the input current is within a weaker range e. By decreasing the effective capacitance, charge pump generates a weaker charge for preventing overloading, but produces less noise. For example, in some embodiments, capacitors A and B may have capacitances of 15 f and f, respectively.
By coupling capacitors in parallel, an effective capacitance of f is created, which increases the amount of produced charge by a multiple of In some embodiments, if the input current exceeds the high signal range e.
Negative charge pump , in one embodiment, is adapted to generate a negative charge that drives a current to DAC from node In the illustrated embodiment, charge pump is adapted to generate negative charge, by charging one or both of capacitors using voltage source B and coupling them to ground using switch D. By charging and coupling capacitors , charge pump inverts the voltage of source B and generates a negative charge. For example, in some embodiments, if source B has a voltage of 1.
Similar to charge pump , charge pump , in one embodiment, is adapted to adjust the amount of capacitance used to generate the negative charge based on the strength of the input current of ADC In some embodiments, capacitors may have a lesser capacitance than e.
In many instances, having a lesser capacitance reduces the average DAC-noise-contribution power directly proportional to the size of the capacitors. In one embodiment, charge pumps and are adapted to generate their respective charges simultaneously regardless of the output of comparator One of the charges is then selected based on the output of comparator , and provided to node For example, in one embodiment, when comparator outputs a logical 1, positive charge pump is adapted to steer its charge into the input path at node , and negative charge pump is adapted to steer its charge into, e.
On the other hand, when the output of comparator is a logical 0, the reverse occurs—i. By generating both charges in some embodiments, DAC draws a relatively uniform load that is substantially independent of whether it is providing a positive or negative charge.
Generating both charges can also allow slower settling from the reference supply. As another advantage, ADC , in some embodiments, does not have to make a comparator decision a half-clock earlier to determine whether to generate a positive or negative charge on a single capacitor.
The decision where to steer the charge pump outputs, either into the signal input or a load e. This allows longer clock delay through the two integrators, which has some settling benefits, allowing faster settling time relatively high clock speeds for a given integrator bias. In one embodiment, in order to assure that the input stays the same value independent of the integrator output, the input is a two stage or higher integrator which can also take longer to settle. For symmetric DACs, low gain, single stage integrators may be used; the DAC errors arising from input offset dependent on previous history may not cause distortion, only an ADC gain error.
As discussed above, analog integrator is one embodiment of a delta-sigma first integrator that is adapted to perform a first integration of a voltage at node In the illustrated embodiment, integrator includes an operational amplifier Op Amp Amplifier is coupled to a feedback loop that includes metal-oxide-silicon MOS capacitors A and B, a reset switch A, and a selection switch B.
Amplifier is also coupled to reference voltage source The output of amplifier is coupled to another MOS capacitor , which, in turn, is coupled to switches A-D and voltage sources A and B. Amplifier , in one embodiment, is adapted to amplify the voltage difference between the voltage at node and the voltage provided by source In one embodiment, reset switch A is adapted to reset amplifier at the beginning of an integration period by coupling the input and output of amplifier In the illustrated embodiment, MOS capacitor is coupled to the output of amplifier to cancel or substantially cancel distortion created by capacitors In one embodiment, capacitor is identical or substantially identical to MOS capacitors , and is adapted to have the same bias voltage as capacitors In some embodiments, integrator is adapted to change the effective capacitance of the feedback loop based on the input current of ADC , or the gain of DAC , which is dependent upon the input current, in some embodiments.
In the illustrated embodiment, integrator is adapted to change the effective capacitance by using selection switch A. In one embodiment, if the input current is within a weaker range e. If the input current is within a stronger range e. By changing the effective capacitance of the feedback loop in this manner, integrator , in some embodiments, adjusts the noise produced by the feedback loop while preventing overloading of integrator In one embodiment, integrator uses a medium threshold NMOS on a single-ended input as opposed to a differential input which has an input threshold of, say, 0.
It functions as a relatively low noise input with the positive input referenced from an AC signal perspective to Vss or ground potential with a DC offset equal to the NMOS gate threshold.
Because the input is not a differential transistor pair in the illustrated embodiment, but uses a single transistor, it exhibits lower noise levels and better headroom, and has faster gain bandwidth for the same bias current, thus making a high gain, multi-stage integrator easier to stabilize. Although balanced differential inputs are considered to provide high noise rejection, they do so if the signal input source has both a balanced impedance to ground and balanced pickup of noise.
The input is the most sensitive part of the system, where noise immunity is desirable. However, photodiodes are inherently single ended or asymmetric both in impedance and electrostatic noise pickup. Thus, a small integrated photodiode can be not only cheaper if less than one third the area but also outperform an external photodiode. Consequently, a single ended amplifier structure for the first integrator in a photo ADC delta-sigma application may achieve better noise performance with less power compared, with a differential structure when receiving an input signal from an integrated photodiode.
In addition, the single ended amplifier structure generally is simpler and higher performing in relatively low voltage applications, say, under 1. In some embodiments, integrator may use differential input circuitry, depending on considerations such as the desired performance and application, etc.
Because the DAC impedance is asymmetric, integrator may have a relatively fast-settling, high-voltage, high-transconductance gain, so that there is relatively low data-dependent offset on the input which would otherwise modulate the charge input.
A conventional single stage cascade amplifier fails to achieve sufficient integrator gain or gain bandwidth typically desired. As discussed above, analog integrator is one embodiment of a delta-sigma second integrator that is adapted to perform a second integration of a voltage at node In the illustrated embodiment, integrator includes an operational amplifier that is coupled to a voltage source and a feedback loop. The feedback loop includes MOS capacitor and a reset switch In one embodiment, amplifier is adapted to have less amplifier gain than amplifier described above.
In one embodiment, MOS capacitor has smaller capacitance than capacitors In the illustrated embodiment, amplifier is also coupled to a capacitor , which, in turn, is coupled to switches A and B. In one embodiment, integrator is adapted to shift the input voltage of amplifier to a center value by using capacitor In one embodiment, MOS capacitor , due to its very thin gate oxide, is smaller in area than a more-linear field oxide capacitor. Linearity correction may not be used when using a MOS capacitor on the second integrator since the output decision may happen at the same voltage.
The linearity of the feedback capacitor on the integrator may have no effect on the total charge input plus or minus. In other words, it may take the same negative charge input as the previous charge input to return the integrator value back to the same comparator switching voltage. In one embodiment, the second integrator feedback capacitor has sufficient capacitance in both directions to prevent overload before the delta sigma feedback has to time to correct.
Capacitor may also use shifted biasing since MOS capacitors have a unidirectional bias voltage to maintain high capacitance unlike field oxide capacitors which may have plus or minus voltage. As discussed above, in one embodiment, comparator is a delta-sigma latched comparator that is adapted to compare the output of integrator with a reference voltage V ref. In the illustrated embodiment, the reference voltage is provided by voltage source The input of comparator is also coupled to over-range OVR detector OVR detector includes elements and a latch Elements A and B are coupled to respective voltage sources A and B.
In one embodiment, OVR detector is adapted to detect if the output of integrator is about to saturate, which occurs if the delta-sigma loop cannot drive the input signal to zero. If such an event occurs, digital integrators and may not accurately reflect the signal input value. In one embodiment, detector is adapted to latch any analog over range that occurs on integrator In some embodiments, detector may be double buffered such that the output latch holds the previous measurement value until a new measurement is finished.
As discussed above, in one embodiment, digital integrator is adapted to integrate the output values produced by comparator over a specified integration period. In the illustrated embodiment, integrator includes an accumulator that receives a clock signal and a reset signal Accumulator , in one embodiment, is adapted to calculate the number of times comparator outputs a logical 1 referred to as a count over a specified integration period.
In one embodiment, accumulator is adapted to add the current output of comparator to a running total value in response to a rising edge of clock signal In one embodiment, accumulator may be adapted to store a maximum of counts 9-bit value and receive a 20 MHz clock signal. In one embodiment, integrator is adapted to reset accumulator at the end or beginning of an integration period in response to receiving reset signal As will be described below in FIGS.
In other embodiments, other integration periods and count values may be used. In some embodiments, the integration period and count value may be specified by a user, e. In some embodiments, the integration period may be increased or decreased based on the strength of the input received by ADC e.
As discussed above, in one embodiment, digital integrator is adapted to perform a second integration based on the output of integrator over the specified integration period. Accumulator , in one embodiment, is adapted to add the value stored in accumulator to a stored running total. In one embodiment, accumulator adds a value for each clock cycle of clock signal over the specified integration period.
In one embodiment, accumulator may be adapted to store up to bit value and receive a 20 MHz clock signal. In one embodiment, accumulator is adapted to provide the current total to a storage buffer at the end of the integration period. In the illustrated embodiment, diagram includes specific values for various structures described above. In other embodiments, other suitable values may be used. In the illustrated embodiment, diagram also includes a switched capacitor network , switched capacitor network , and LED unit Switched capacitor network , in one embodiment, is adapted to provide a first-order feedback path, which facilitates delta-sigma loop stability.
Switched capacitor network , in one embodiment, is configured as a voltage input and the bypass path for an external current source. In one embodiment, network , combined with a secondary input MUX, allows ADC to be reused with a relatively small amount of additional circuitry for other functions, such as relatively accurate voltage, current, and resistor measurements on both internal and external devices. For example, in one embodiment, ADC can measure in voltage mode, by selecting the appropriate MUXs, the internal temperature reference, the Vdd supply voltage, or an external voltage presented on an unused IO pin.
In one embodiment, if ADC is in current mode and appropriate MUX are set, it may measure the current from an external photodiode for an auxiliary photo processing application, or it may measure a resistor allowing a determination of its value which may be used for setting a firmware controlled parameter, as desired.
LED unit , in the illustrated embodiment, includes an LED and a driver illuminating an object, the reflection of which is measured by a sequence of measurement cycles. In the illustrated embodiment, diagram includes measurement sequencer , DAC control unit , and input muxes A and B. In other embodiments, ADC may be configured differently than shown. Measurement sequencer , in one embodiment, includes control logic that is adapted to implement a state machine, with a set of counters and various logic circuitry.
In one embodiment, sequence is adapted to perform the control sequence shown in the timing diagrams described below in conjunction with in FIGS. In some embodiments, sequencer may communicate using the following control signals:. It is reset when the data are read. It is a latched and reset when read. This bypasses the measurement sequencer and couples to the analog delta-sigma portion of ADC In the embodiment shown, the ADC sequencer powers up the analog section automatically. The Program Divide may allow the option of reducing the frequency of the ADC clock signal in order to increase the integration period and hence increase the sensitivity of ADC , as described above.
In one embodiment, with the over-sampled clock signal and the command inputs above, measurement sequencer controls the following blocks: the analog Delta-sigma, DAC , digital integrators and , the data output buffer, and the OVR buffer To control these blocks, measurement sequencer , in some embodiments, uses the following control lines:.
DAC control unit , in one embodiment, includes logic that is adapted to coordinate operation of DAC based on the output of comparator In one embodiment, control unit is adapted to control the DAC positive or negative charge on each pulse, depending on whether the comparator output is a logical 0 or 1 and if fdac 0 is asserted. Primary Input MUX A, in one embodiment, provides logic control for the primary input multiplexing, where either 1 of the 3 photodiodes, no input, external current input, or voltage input is determined as a function of control inputs from the main controller logic or circuitry at higher levels of control logic hierarchy.
In some embodiments, ADC may be adapted to use timing parameters specified by diagram if ADC is adapted to measure light received by a photodiode. In other embodiments, ADC may be adapted to use different timing parameters. In one embodiment, when ADC is to make a measurement, it powers up and then waits 31 clocks for biases to settle and stabilize.
In some embodiments, system firmware can also manually power up the ADC, as desired. After the power up delay, system , in one embodiment, configures the signal input to whatever photodiode or voltage or current input that is to be measured.
Then, ADC , in one embodiment, starts the pre-charge period. In the pre-charge period, the analog reset, in one embodiment, is released e. In some embodiments, this pre-charge period is programmable. In one embodiment, following the pre-charge, the analog reset signal is asserted, and the DAC forced 0 state is released, thus starting the programmable duration recovery period. The recovery period allows the photodiode to recover from the minority carriers pulse tail decay of the pre-charge or the previous LED reflectance or previous ADC measurement.
Note that the recovery period settling prevents errors between the first measurement and subsequent measurements because of previous events. In one embodiment, at the end of the recovery period, the measurement period starts with the release of both the analog reset on the integrators and release of reset on the digital integrators and In one embodiment, after counts the measurement ends and the digital integrator is read into the output buffer and ADC data ready bit is set.
In one embodiment, the sequence then powers down, or continues with the next measurement cycle again, as desired. In some embodiments, a calibration measurement may be made prior to performing one or more measurements. In one embodiment, the calibration is an ADC measurement cycle with all inputs off. This ADC calibration may measure the residual offset or zero value of the ADC, which, in one embodiment, is about one quarter of the full scale 2 17 , or about 2 In one embodiment, this calibration value is subtracted from the measurements.
Note that, typically, it does not matter where in a sequence of measurements the calibration is made. Furthermore, note that in some embodiments, the calibration has relatively small temperature drift, for example, about ten counts per degree Celsius. Consequently, in some embodiments, one may perform the calibration relatively infrequently, if convenient or desired.
As discussed above, in some embodiments, system may be adapted to implement a proximity-sensing device that is adapted to measure an amount of light reflected from an object, where an LED light source provides the light. In one embodiment, system is adapted to determine an amount of reflected light by taking a first measurement that samples ambient light without turning on the LED. System may then take a second measurement that samples both the ambient light and light produced by the LED.
System may then subtract the first measurement from the second measurement to determine the amount of reflected. In such embodiments, ADC may be adapted to use timing parameters specified by diagram for a single-calibration proximity sequence. In the illustrated embodiment, diagram shows DC performing an ambient calibration cycle i. In one embodiment, the input of ADC stays on the same photodiode input or multiplexed input.
With this proximity sequence, the calibration reading includes both the ADC offset and the ambient level which represents the background light level , while the proximity measurement includes the ADC offset, plus the ambient level and the proximity reflection. In one embodiment, system reads both values and subtracts the ambient calibration from the proximity measurement to determine the actual reflection component from the strobed LED.
In the illustrated embodiment, each measurement uses an integration period of In other embodiments, other integration periods may be used. In some instances, a Compact fluorescent inverters CFLs or electronic ballasts may range from 30 KHz to 60 KHz, while long tube fluorescent electronic ballasts may operate as low as 20 KHz. These inverters typically produce triangle optical waveforms that are folded to twice the inverter frequency.
Unsynchronized, a measurement pulse that is at least the width of one half cycle of the electronic ballast inverter will generally reduce the integrated noise to less than one fifth of the peak to peak value. The relatively short This method works for both flicker and sunlight flutter since both have relatively low higher frequency components relative to their fundamentals.
For example, with flicker noise, the maximum rate of change occurs on the center slope of the Hz cycle and is about 1. With a Lux incandescent and a Due to the shorter integration period of But this is still lower than the already 80 fold reduced flicker noise at pA.
In this example, the flicker noise can be reduced by another 80 fold by using the dual calibration proximity sequence, which determines the slope of the ambient. Of course, one may continue to add ambient calibration measurements to determine the slope of the slope, etc. In effect, one may apply Taylor polynomial expansion to flicker noise prediction. Typically, this process involves no more than two calibration periods described below in conjunction with FIG.
Note that the dual calibration mode adds about 8 dB of noise over a single calibration. In some embodiments, the dual calibration mode is not used unless it provides a relatively significant improvement for flicker and flutter noise e. In some embodiments, it is possible to further improve the ADC resolution signal-to-noise by repetitively integrating a relatively long series of relatively short calibration and proximity cycles.
For example, in one embodiment, making about 1, measurement cycles of two calibration periods and one proximity over ms and digitally integrating the results improves the resolution by the square root of the number of measurement cycles, or about 36 fold another 5 bits of resolution.
Since the single cycle signal-to-noise resolution is 15 bits, this technique increases signal-to-noise resolution to 20 bit by using relatively simple digital integration.
The improvement in this example is comparable to what one may achieve with two relatively long 50 ms integration measurement periods, assuming the absence of flicker or flutter noise and also assuming the ADC converter has 20 bits of resolution. The bit resolution over the 50 ms integration measurement period for a first-order delta-sigma ADC difficulties achievable, using a 20 MHz clock. However, the flicker and flutter noise still pose problems.
Furthermore, note that reducing the pulse width on a first-order delta system to reduce power or reduce measurement period degrades range. In some embodiments, for lower light conditions, the clock signal of the second-order proximity ADC system may be reduced in order to extend the total integration time. This may be warranted when the lowest bits of the 17 bit, in one embodiment, delta-sigma converters are not noisy, suggesting that both shot and other noise sources are below the minimum ADC resolution.
By extending the integration period by slowing the clock , more total light is gathered, but the charge steps remain the same.
Typically, the This gives a linear increase in signal-to-noise with increasing integration time, rather than a square root increase, if the noise is less than the ADC minimum resolution. Once the noise exceeds the minimum resolution, as the pulse width is increased, the integrated signal-to-noise will increase with the square root of the period.
Note that widening the LED period increases total power but, beyond a range of, say, several meters, the measurement period can be typically ten times longer, on the order of ms or more, since at these ranges the application is usually to detect body or object bulk motion, rather than, for example, faster hand commands.
Although the ADC integration period per measurement, in some embodiments, may be counts, which in the second-order delta-sigma converters may provide a count range, shorter or longer count integration periods can be used by using a programmable counter, as desired, to replace the fixed counter, which controls the integration period.
This allows either higher sampling rate due to shorter measurement periods with reduced resolution, or slower sampling rates with higher resolution, as desired. Sampling these above their Nyquist rate and filtering them appropriately may entail a minimum measurement sampling rate of 60 KHz to KHz, or a maximum sampling period of In one embodiment, this can be achieved by over sampling clock rate of 20 MHz and reducing the counts during the integration period to or counts.
The digital integrator structure may remain the same. For example, with a count integration period, the output range, in one embodiment, may span 13, counts, or somewhat less than 14 bits. By digitizing the input signal, digital filtering and signal processing become possible, which facilitates optimizing the performance of one-way IR remote receivers with relatively high sensitivity.
In the illustrated embodiment, diagram shows a first calibration cycle A, a second calibration cycle B, and a proximity cycle In one embodiment, the proximity measurement dual calibration sequence, which is similar to the single calibration sequence shown in diagram , except that an additional calibration cycle B is added. In one embodiment, this calibration measurement may be identical to the first one.
Again, note that the three cycles differ in that during the last proximity cycle the LED strobe is enabled. With two ambient calibration cycle measurements, system , in one embodiment, is adapted to measure the slope of the ambient change to more accurately predict its value during proximity. Generally, this dual calibration proximity may be used in environments that have relatively high levels of ambient flicker, flutter, or both.
Although for both proximity sequences the LED strobe is shown as the last event, in some embodiments, proximity sequences may be at the beginning or between the dual calibration values, as desired. Accordingly, the slope correction formula may change if the sequence is different for the dual calibration sequence. It is typically desirable to both minimize and keep uniform the delay between calibration and proximity measurement in order to accurately cancel the changing ambient.
This is a reason that, in one embodiment, an ADC digital controller may have control over the sequence in order to remove firmware dependent timing and to reduce firmware overhead. In some embodiments, system may duplicate the proximity measurements by doing two or three single measurements sequentially and controlling the LED. Method is one embodiment of a method that may be performed by ADC to convert an analog input signal into a digital signal. In some instances, performing method may produce a higher signal-to-noise ratio by reducing the presence of noise in the input signal and noise created by an ADC.
In some embodiments, steps - may be performed in a different order than shown.
0コメント